Many integrated circuit (IC) designs use glitch-free multiplexers to dynamically switch a clock input to a given circuit in response to operating conditions or modes. As is known, a glitch is generally understood to be a very short duration change of value. For example, in the case of a 50% duty cycle clock (i.e., the clock is at a high logic level for ½ period and a low logic level for ½ period), the glitch may be a pulse on the clock line of significantly less than ½ period duration. Most glitch-free, clock multiplexing circuits require that the phase and frequency relationships of all input clocks be known in order to ensure glitch-free operation. In some IC designs, one or more of the input clocks may have unknown phase and frequency relationships to other known clocks in the design. If the input clock is unknown, a conventional edge detection circuit that detects the edge of an unknown signal typically uses a sample clock of at least twice the highest expected frequency of the input clock, but with a high probability of propagating meta-stable (i.e., ambiguous) states through down-stream logic as a result of the unknown phase relationship of the clocks.
Some IC designs incorporate a standard back-to-back flip-flop, meta-stability resolution circuit on the input clock. Such designs typically require a sample clock of at least eight (8) times the highest expected frequency of the input clock to produce an edge detection signal during the corresponding low or high phase of the input clock signal. Such a high frequency multiplier may cause unacceptable meta-stability resolve probability at the meta-stability flip-flops.